1. Field of the Invention
The present invention relates to a resistance element and a capacitance element which are applied to a semiconductor integrated circuit having a 3-dimensional stacked layer structure.
2. Description of the Related Art
Recently a technique of stacking elements on a semiconductor substrate to form a 3-dimensional structure is developed to achieve high integration and high performance of a semiconductor integrated circuit.
For example, a BiCS (Bit Cost Scalable) technique is a well-known technique of achieving large capacity to curb costs by the 3-dimensional structure (for example, see “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory” 2007 Symposium on VLSI Technology Digest of Technical Papers. p 14).
A nonvolatile semiconductor memory (hereinafter referred to as BiCS memory) to which the BiCS technique is applied is not a simple 3-dimensional structure, but the BiCS memory enables bit cost scalability by devising a device structure and a process technique. In the bit cost scalability, bit cost is reduced in proportion with an increase of the number of stacked layers.
For example, when the BiCS technique is applied to a NAND flash memory (hereinafter referred to as BiCS-NAND flash memory), the number of cells constituting a NAND string is vertically increased by increasing the number of stacked layers, thereby realizing a memory capacity that largely exceeds a memory capacity limit of a NAND flash memory having a 2-dimensional structure.
However, in a semiconductor memory such as the BiCS memory having the 3-dimensional stacked layer structure, although a memory cell array is 3-dimensionally formed, a 3-dimensional peripheral circuit is not sufficiently studied yet.